1. Field
Various exemplary embodiments of the present invention relate to a semiconductor memory system and an operating method thereof.
2. Description of the Related Art
In general, semiconductor memory devices are classified into volatile memory devices, such as Dynamic Random Access Memory (DRAM) and Static RAM (SRAM), and non-volatile memory devices, such as Read Only Memory (ROM), Mask ROM (MROM), Programmable ROM (PROM), Erasable PROM (EPROM), Electrically EPROM (EEPROM), Ferromagnetic RAM (FRAM), Phase change RAM (PRAM), Magnetic RAM (MRAM), Resistive RAM (RRAM) and flash memory.
Volatile memory devices lose their stored data when their power supplies are interrupted, whereas non-volatile memory device retain their stored data even when their power supplies are interrupted. Non-volatile flash memory devices are widely used as storage mediums in computer systems because of their high program speed, low power consumption and large data storage capacity.
In non-volatile memory devices, especially in flash memory devices, the data state of each memory cell depends on the number of bits that the memory cell can program. A memory cell storing 1-bit data per cell is called a single-bit cell or a single-level cell (SLC). A memory cell storing 2-bit data per cell is called a multi-bit cell, a multi-level cell (MLC) or a multi-state cell. And a memory cell storing 3-bit data per cell is called a triple-level cell (TLC). The MLC and TLC are advantageous for high integration. However, as the number of bits programmed in each memory cell increases, the reliability decreases and the read failure rate increases.
For example, when k bits are to be programmed in a memory cell, one of 2k threshold voltages is formed in the memory cell. Due to minute differences between the electrical characteristics of memory cells, the threshold voltages of memory cells programmed for the same data form threshold voltage distribution. Threshold voltage distributions correspond to 2k data values corresponding to k-bit information, respectively.
However, a voltage window available for threshold voltage distributions is finite. Therefore, as the value k increases, the distance between the threshold voltage distributions decreases and the neighbouring threshold voltage distributions overlap. As the neighbouring threshold voltage distributions overlap, read data may include error bits.
FIG. 1 is a threshold voltage distribution schematically illustrating program and erase states of a 3-bit TLC non-volatile memory device.
FIG. 2 is a threshold voltage distribution schematically illustrating program and erase states due to characteristic deterioration of the 3-bit TLC non-volatile memory device.
In a TLC non-volatile memory device, e.g., a TLC flash memory device capable of storing 3-bit data (i.e., k=3) in a single memory cell, the memory cell may have one of 23, i.e., 8 threshold voltage distributions.
Threshold voltages of memory cells programmed for the same data form the threshold voltage distribution due to characteristic differences between memory cells. In the 3-bit TLC non-volatile memory device, as illustrated in FIG. 1, threshold voltage distributions are formed in correspondence with the data states including 7 program states ‘P1’ to ‘P7’ and an erase state ‘E’. FIG. 1 shows an ideal case in which threshold voltage distributions do not overlap and have sufficient read voltage margins therebetween.
Referring to the flash memory example of FIG. 2, the memory cell may experience charge loss in which electrons trapped at a floating gate or tunnel oxide film are discharged over time. Such charge loss may accelerate when the tunnel oxide film deteriorates by iterative program and erase operations. Charge loss results in a decrease in the threshold voltages of memory cells. For example, as illustrated in FIG. 2, the threshold voltage distribution may be shifted left due to charge loss.
Further, program disturbance, erase disturbance and/or back pattern dependency also cause increases in threshold voltages. As characteristics of memory cells deteriorate, neighbouring threshold voltage distributions may overlap, as illustrated in FIG. 2.
Once neighbouring threshold voltage distributions overlap, read data may include a significant number of errors when a particular read voltage is applied to a selected word line. For example, when a sensed state of a memory cell according to a read voltage Vread3 that is applied to a selected word line is on, the memory cell is determined to have a second program state ‘P2’. When a sensed state of a memory cell according to a read voltage Vread3 applied to a selected word line is off, the memory cell is determined to have a third program state ‘P3’. However, when neighbouring threshold voltage distributions overlap, a memory cell that has the third program state ‘P3’ may be erroneously determined to have the second program state ‘P2’. In short, when the neighbouring threshold voltage distributions overlap as illustrated in FIG. 2, read data may include a significant number of errors.
What is therefore required is an improved scheme for precisely reading data stored in memory cells of a semiconductor memory device.